In general, a level shifter is used for transmitting signals between circuits coupled to difference voltage sources.
Please refer to FIG. 1 which schematically illustrates a conventional level shifter. The level shifter includes PMOS transistors P6 and P7, NMOS transistors N6 and N7, and Not gates 10 and 20.
The level shifter is designed to function like a cross-coupled level converter (CCLC). As shown, the sources of the PMOS transistors P6 and P7 are coupled to a high voltage source VDDH; the gate of the PMOS transistor P6 is coupled to the drain of the PMOS transistor P7; the gate of the PMOS transistor P7 is coupled to the drain of the PMOS transistor P6; the drain of the NMOS transistor N6 is coupled to the drain of the PMOS transistor P6; the source of the NMOS transistor N6 is grounded; the drain of the NMOS transistor N7 is coupled to the drain of the PMOS transistor P7; the source of the NMOS transistor N7 is grounded; the Not gate 10 is coupled to a low voltage source VDDL; a signal input IN is coupled to the gate of the NMOS transistor N7 as well as the input end of the Not gate 10; the output end of the Not gate 10 is coupled to the gate of the NMOS transistor N6; the Not gate 20 is coupled to the high voltage source VDDH; the drain of the NMOS transistor N7 is coupled to the input end of the Not gate 20; and the output end of the Not gate 20 serves as the signal output OUT. Therefore, it is thus understood the high level of the signal input IN is the level of VDDL, while the low level is the ground level. On the other hand, the high level of the signal output OUT is the level of VDDH, while the low level is the ground level.
When the signal input IN is switched from the low level to the high level, the NMOS transistor N6 is turned off, and the NMOS transistor N7 is turned on so that the Not gate 20 receives a signal at the low level but outputs the signal at the high level. On the other hand, when the signal input IN is switched from the high level to the low level, the NMOS transistor N7 is turned off, and the NMOS transistor N6 is turned on. Meanwhile, the PMOS transistor P7 is turned on, and the PMOS transistor P6 is turned off so that the Not gate 20 receives a signal at the high level but outputs the signal at the low level.
The above-described level shifter is simple in design. However, it suffers from a number of drawbacks. For example, the cross-coupled PMOS transistors P6 and P7 may have a racing phenomenon when the state at the signal input I changes. The racing phenomenon would adversely affect the duration for the nodes A and B to reach the steady state so as to result in long propagation delay. In addition, the racing phenomenon would make the level shifter consume much power. Furthermore, since the signal input IN is generally switched from the low level to the high level faster than from the high level to the low level, a time non-balance problem for signal conversion would occur.
Another level shifter is illustrated in FIG. 2, which describes a prior art taught in U.S. Pat. No. 7,145,363. The level shifter includes PMOS transistors P8 and P9, NMOS transistors N8, N9, N10 and N11, and Not gates 30, 40 and 50. The level shifter has also a cross-coupled level converter (CCLC) architecture. As shown, the sources of the PMOS transistors P8 and P9 are coupled to a high voltage source VDDH; the gate of the PMOS transistor P8 is coupled to the drain of the PMOS transistor P9; the gate of the PMOS transistor P9 is coupled to the drain of the PMOS transistor P8; the drain of the NMOS transistor N8 is coupled to the drain of the PMOS transistor P8; the source of the NMOS transistor N8 is grounded; the drain of the NMOS transistor N9 is coupled to the drain of the PMOS transistor P9; the source of the NMOS transistor N9 is grounded; the input end of the Not gate 30 is coupled to a signal input IN; the output end (the node C) of the Not gate 30 is coupled to the gate of the NMOS transistor N8 and the input end of the Not gate 40; the output end (the node D) of the Not gate 40 is coupled to the NMOS transistor N9; the output end of the Not gate 50 is coupled to the drain of the NMOS transistor N9; the output end of the Not gate 50 serves as the signal output OUT. Furthermore, the NMOS transistors N10 and N11 function as two auxiliary pull-up devices of the level shifter. The gate of the NMOS transistor N10 is coupled to the node D; the drain of the NMOS transistor N10 is coupled to the high voltage source VDDH; the source of the NMOS transistor N10 is coupled to the drain of the PMOS transistor P8. The gate of the NMOS transistor N11 is coupled to the node C; the drain of the NMOS transistor N11 is coupled to the high voltage source VDDH; the source of the NMOS transistor N11 is coupled to the drain of the PMOS transistor P9.
The level shifter of FIG. 2 exempts from the racing problem mentioned above. In other words, when the signal input IN is switched from the low level to the high level, the node C is at the low level while the node D is at the high level. Meanwhile, the auxiliary pull-up device N10 is turned on to have the level at the node A rapidly pulled up to the high-level ready state. Likewise, when the signal input IN is switched from the high level to the low level, the node C is at the high level while the node D is at the low level. Meanwhile, the auxiliary pull-up device N11 is turned on to have the level at the node B rapidly pulled up to the high-level ready state. In this way, the racing problem is eliminated. However, since the auxiliary pull-up devices are both NMOS transistors and directly coupled to the high voltage source, an electrostatic discharge (ESD) path would be formed and the pull-up devices are likely to be damaged.